Formal Verification: Key technical points 2022

About this Course

Formal verification, especially Formal Signoff, covers a wide range of technologies and has relatively high requirements for users. There is a big difference between the verification work done by Formal verification engineers and traditional simulation engineers. The main job of the traditional simulation verification engineer is to write test cases to verify the design function, while most of the work of the formal verification engineer is to model the design behavior, which requires the formal verification engineer to understand the design functions deeply.

This course is a fundamental introduction to all important technical points in the current field of Formal verification. For each technical point, the course mainly focuses on a brief introduction and concepts but no in-depth discussion. By learning the basics of these technical points, students will have a preliminary understanding of Formal verification technology. This course can be used as the first and necessary ladder for everyone who wants to step into the field of Formal verification. Moreover, it will lay an indispensable foundation for students to apply Formal verification technology to practices in the future.

Course Objectives

This course answers many basic questions about the field of formal verification, explains the basic principles of the underlying technology of formal verification, proposes the latest formal signoff methodology, and expounds the technical development direction in the field of formal verification. By taking this course, you will have a certain understanding of formal verification techniques, as well as some basic knowledge of formal methodology. Let’s first look at some of the basic goals of this course.

• In order to use formal verification reasonably and effectively, it is often necessary to consider the entire verification process as a whole to play a role of formal verification. It is very necessary to apply formal methods to the verification process in a systematic process.

• The basic principle of Formal verification is to verify the functional correctness of the design based on logical derivation and mathematical proof. Formal tools model the design’s behavior. On the compiled design model, through the traversal exhaustive feature, Formal tools analyze whether the properties are consistent with the design’s behavior in all reachable state space cycle by cycle.

• The goal of formal verification is in the form of property checking. The features of the design function are abstractly extracted one by one according to the description of the Spec, and these extracted features are translated and expressed through a property-based language. Then build a platform environment for property-based formal testing to compare with the functions in the design RTL code to verify the correctness of the design functions.

• Formal verification, due to its fully proven nature, enables full functional verification of design modules and can be delivered as a final functional sign-off. A comprehensive Formal signoff methodology is provided in this course.

• The complexity is a significant problem in Formal Signoff. In the Formal Signoff flow, users have to spend a lot of time and effort analyzing and solving the problem of complexity in the design. This course explains the leading causes of complexity in a design, the relationship between the complexity and the properties, and how to analyze the impact of the complexity in Formal verification.

• Coverage is another significant problem in Formal Signoff. The results of assertions represent the functional correctness of Formal verification. However, verification is a matter of confidence, and a complete verification flow must consider completeness. Regardless of whether it is the Formal Signoff with full proof or the Signoff with coverage, the coverage plays a vital role in the Formal Signoff flow.

• In addition to sign-off, there are many simple and easy-to-use formal applications of formal verification. These out-of-the-box applications provide corresponding formal solutions for different verification problems, which enable beginners or engineers without formal verification technical backgrounds to quickly and efficiently solve some problems encountered in verification.

Course Agenda

• Formal Verification Overview

In this chapter, we will introduce what formal verification is, its historical perspective, current trends, why it is needed, its requirements, its challenges, formal verification tool vendors, a comparison of the main vendors’ tool features, and Formal capability levels.

• Formal Analysis

In this chapter, we will introduce the formal verification framework, compiling a formal model, formal model concepts, applying a proof algorithm, formal proof results.

• Property Checking

In this chapter, we will cover formal property verification, property checking, property checking guidelines, end-to-end property checking, constraint development.

• Formal sign-off

In this chapter, we will cover ROI and criteria of formal signoff, formal signoff testbench, formal signoff environment, formal sign-off with full prove flow, formal sign-off with coverage flow.

• Complexity

In this chapter, we will cover Cone of Influence(COI), the definition of complexity, measurement of complexity, properties and complexity, complexity analysis.

• Coverage

In this chapter, we will introduce definition of code and functional coverage, metrics types of coverage, controllability and observability of coverage, measurement of formal coverage, criteria of formal coverage.

• Formal Verification Applications

As the out-of-the-box nature of formal verification applications is more and more accepted, it is becoming popular in the verification field. At present, the major formal verification tool suppliers are constantly launching their own formal verification applications. In this chapter, we will introduce some of the most used formal verification applications today.

Who this course is for:

• Formal Engineers
• RTL Design Engineers
• IP Designers
• Verification Engineers
• DV ManagersSystem Architects
• DV Managers