High-Level Synthesis for FPGA, Part 1-Combinational Circuits
Learn the basics of High-Level Synthesis (HLS) and how to design combinational logic circuits using C/C++ language. This course covers the HLS design flow for FPGAs and teaches you how to work with Xilinx Vitis-HLS and Vivado suite Toolsets. You will also learn how to generate RTL hardware IPs using Vitis-HLS and implement two exciting projects. This course is perfect for hardware and software engineers, as well as lecturers, researchers, and digital logic enthusiasts who want to utilize FPGAs for their exceptional performance and low power consumption.
What you’ll learn
- Designing combinational logic circuits with C/C++ language using the HLS approach
- Understanding the basic concepts of High-Level Synthesis (HLS)
- Using HLS concepts for designing combinational logic circuits
- HLS design flow for FPGAs
- Working with Xilinx Vitis-HLS and Vivado suite Toolsets
- How to generate RTL hardware IPs using Vitis-HLS
- Writing C-testbench in HLS
- Implementing two exciting projects with HLS
This course is an elementary introduction to high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.
It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first to build the HLS design flow and skills along with the digital logic circuit concepts from scratch. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.
This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits. The other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.
Who this course is for:
- Hardware engineers
- Software engineers who are interested in FPGAs
- Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
- Digital Logic enthusiasts
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